library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sev_seg is
port (
      clk : in std_logic;
      p1_inc, p2_inc : in std_logic;
        segment1 : out std_logic_vector(6 downto 0);  -- 7 bit decoded output.
		  segment2 : out std_logic_vector(6 downto 0)
    );
end sev_seg;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of sev_seg is

signal p1, p2: std_logic_vector(3 downto 0) := "0000";

begin
process (p1_inc,p2_inc)
begin
if (p1_inc = '1') then
 p1 = p1 + 1;
 elsif  (p2_inc = '1')
 p2 = p2 + 1;
 end if;
end process;


begin
process (clk,p1,p2)
BEGIN
if (clk'event and clk='1') then
case p1 is
when "0000"=> segment1 <="0000001";  -- '0'
when "0001"=> segment1 <="1001111";  -- '1'
when "0010"=> segment1 <="0010010";  -- '2'
when "0011"=> segment1 <="0000110";  -- '3'
when "0100"=> segment1 <="1001100";  -- '4'
when "0101"=> segment1 <="0100100";  -- '5'
when "0110"=> segment1 <="0100000";  -- '6'
when "0111"=> segment1 <="0001111";  -- '7'
when "1000"=> segment1 <="0000000";  -- '8'
when "1001"=> segment1 <="0000100";  -- '9'
 --nothing is displayed when a number more than 9 is given as input.
when others=> segment1 <="1111111";



end case;

case p2 is
when "0000"=> segment2 <="0000001";  -- '0'
when "0001"=> segment2 <="1001111";  -- '1'
when "0010"=> segment2 <="0010010";  -- '2'
when "0011"=> segment2 <="0000110";  -- '3'
when "0100"=> segment2 <="1001100";  -- '4'
when "0101"=> segment2 <="0100100";  -- '5'
when "0110"=> segment2 <="0100000";  -- '6'
when "0111"=> segment2 <="0001111";  -- '7'
when "1000"=> segment2 <="0000000";  -- '8'
when "1001"=> segment2 <="0000100";  -- '9'
 --nothing is displayed when a number more than 9 is given as input.
when others=> segment2 <="1111111";

end case;

end if;

end process;

end Behavioral;